Compound semiconductors are receiving renewed attention for use as channel materials for advanced ultra large scale integration (ULSI) digital logic applications due to their high electron hole mobility. For example, the InGaAs/InAlAs material system is one of the most promising material systems for this application due to its large conduction-band offsets and high carrier mobility. Schottky-gated InGaAs high electron mobility transistors (HEMTs) grown on InP substrates have produced maximum transconductance gm values over 2 S/mm (see, D. Xu et al., IEEE Elec. Dev. Let., 20, 206 (1999)), and have been shown to compare favorably in terms of a power-delay product (see, D. H. Kim et al., IEDM Tech. Dig., 787, (2005)).
Despite these promising results, for ULSI applications, InGaAs-channel field effect transistors (FETs) will ultimately need to incorporate high dielectric constant (k) dielectrics as the gate dielectric in order to meet current leakage requirements.
Previous work on InGaAs-channel metal oxide semiconductor field effect transistors (MOSFETs) has mainly focused on surface-channel device geometries. See, for example, F. Ren, IEEE. Elec. Dev. Let., 19, 309 (1998). Such devices, however, require the formation of an extremely high quality semiconductor/dielectric interface in order to preserve a low interface state density near the surface-layer conduction band edge.
Despite the above advances in the art, integration of InGaAs-channels for FET applications still requires breakthrough in the following areas (i) surface passivation in conjunction with compatibility with high k gate dielectrics, (ii) quantum well engineering for scalability beyond 22 nm CMOS technology, and (iii) low resistance in the source/drain regions. To date, the applicants are unaware of any prior art III-V compound semiconductor-containing structure that satisfies the three requirements mentioned above.
In view of the above, there exists a need for providing a III-V compound semiconductor-containing heterostructure which can be used as a buried channel for FETs, including MOSFETs.
There also exists a need for providing a III-V compound semiconductor-containing heterostructure which provides (i) surface passivation in conjunction with compatibility with high k gate dielectrics, (ii) quantum well engineering for scalability beyond 22 nm CMOS technology, and (iii) low resistance in the source/drain regions.